Dr. R. K. Navandar
Professor
- rajeshnavandar@jspmjscoe.edu.in
About Me
Qualifications
- M.Tech(Electronics),PhD(E&TC)
Total Experience
- Teaching Experience: 18 Yrs
- Industrial Experience: 2 Yrs
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- Area of Interest: VLSI Design, ASIC & FPGA Design
- Research Interest: Low Power ASIC Design
- Technical Skills: VHDL, CMOS Circuit Design & Layout Design
- Certifications: STA (NPTEL)
- Professional Membership and Contributions: IETE, Worked as a Technical Consultant for einfochip Company,Ahmadbadad
- VLSI Design Digital Electronics Business Management ASIC Design
- SOC Design
- Control System
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| Title of Projects | Research | Duration | Funding Agency | Amount Sanctioned |
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| ASIC Physical Design Training to ME/M.Tech Students at einfochips Pvt Ltd | ASIC Physical Design Projects |
| Held responsibility of overall Coordinator for International Conference on knowledge Discovery in Science and Technology [ICKDST-18]” held at, JSCOE, Pune – 27TH AND 28TH Feb 2018 | International Conference- ICKDST-18 |