About Me
Assistant Professor specializing in VLSI Design and Electronics & Telecommunication with expertise in digital/analog circuits and communication systems. Passionate about low-power VLSI, FPGA/ASIC design, and guiding students in practical and research-oriented learning.
Qualifications
- M.Tech (VLSI Design)
- B.Tech (Electronics & Telecommunication Engineering)
Total Experience
- Teaching Experience: 4 years
- Industrial Experience:
3 years
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- Area of Interest:
VLSI Design, Digital & Analog Electronics, CMOS Circuit Design, Embedded Systems, Signal Processing, Communication Systems, FPGA & ASIC Design.
- Research Interest:
Low Power VLSI Design, ASIC & FPGA Architectures, CMOS Scaling & Nanoelectronics, High-Speed Digital Design, Signal Processing Hardware, Wireless Communication Systems, IoT & Embedded Systems, VLSI for AI/ML Applications
- Technical Skills:
VLSI Design (Digital/Analog), Verilog/VHDL, CMOS & ASIC Design Flow, FPGA Design, STA & Physical Design, Embedded Systems, DSP & Communication Systems, MATLAB/Simulink, Python Programming.
- Certifications:
Certification in VLSI Design & Verification, FPGA Design Certification, Embedded Systems & IoT Certification, MATLAB/Simulink Training, Digital Signal Processing Certification.
- Professional Membership and Contributions:
Member of IEEE and ISTE. Actively participated in technical workshops, conferences, and FDPs in VLSI and communication systems. Contributed to student project guidance, research activities, and curriculum development in emerging areas like VLSI and embedded systems.
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• Network Analysis.
• Electronic Device.
• VLSI Design.
• Digital Signal Processing.
• Data Communication.
• Control system.
• Digital Electronics.
• MicroController.
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Area Optimized S-Box Architecture for Advanced Encryption Standard
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International Journal
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This paper presents an area optimized for composite field arithmetic based SubBytes transformation (Sbox) used in Advanced Encryption Standard (AES) encryption. The proposed architecture is based on pre computation technique. Implementation is proposed on FPGA using Xilinx ISE on XC3S 400-5 and results are shown in the paper.
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2012
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A VHDL Implementation of Low Area Advanced Encryption Standard Processor
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International Journal
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To implement the Sub bytes and Inv sub bytes transformations of the AES algorithm the proposed design employs Combinational logic only for implementing Sub bytes (S-Box) and Inv sub-Bytes (Inverse S Box). The resulting hardware requirements are presented for proposed design and compared by ROM- based and pre-computation technique and improve with these two techniques a new technique is Galois field arithmetic.
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2013
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Implementation of Optimized DES Encryption Algorithm up to 4Round on Spartan 3
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International Journal
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Implementation of Optimized DES Encryption Algorithm up to 4Round on Spartan 3
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2012
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• Industrial Training
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THERMALPOWER STATION
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• Industrial Training
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BSNL
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